Rapid prototyping of digital systems sopc edition / James O. Hamblen, Tyson S. Hall, Michael D. Furman.
Tipo de material:
TextoDetalles de publicación: New York : Springer, c2008Descripción: xvii, 411 p. : il. ; 26 cm. + 1 disco compacto (4 3/4 plg.)ISBN: - 0387726705
- 9780387726700
- TK 7895 .G36 H34
| Tipo de ítem | Biblioteca actual | Biblioteca de origen | Colección | Signatura topográfica | Copia número | Estado | Notas | Fecha de vencimiento | Código de barras | Reserva de ítems | |
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Biblioteca Antonio Enriquez Savignac | Biblioteca Antonio Enriquez Savignac | COLECCIÓN RESERVA | TK 7895 .G36 H34 (Navegar estantería(Abre debajo)) | 1 | No para préstamo | Ing. Telematica | 029125 |
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| TK 7888 .3 R81 2000 Construya su propia PC / | TK7895.E42 W54 Enbedded systems and computer architecture / | TK7895.E42 W54 Enbedded systems and computer architecture / | TK 7895 .G36 H34 Rapid prototyping of digital systems sopc edition / | TK7895.S65 A9395 Automatic speech recognition on mobile devices and over communication networks / | TK7895.S65 R11630 1993 Fundamentals of speech recognition / | TK 7895 .S65 V8891 Voice user interface design / Michael H. Cohen, James P. Giangola, Jennifer Balogh |
Incluye índice
Para disco compacto véase: DC TK 7895 .G36 H34
Tutorial : the 15 minute design -- FPGA development board hardware and I/O features -- Programmable logic technology -- Tutorial sequential design and hierarchy -- FPGA acore library functions -- Using VHDL for synthesis of digital hardware -- Using Verilog for synthesis of digital hardware -- State machine design : the electric train controller -- A simple computer design : the uP 3 -- VGA video display generic using FPGAs -- Interfacing to the PS/2 keyboard and mouse -- Legacy digital I/O interfacing standards -- FPGA robotic projects -- A RISC design : synthesis of the MIPS processor core -- Introducing system on a programmable chip -- Tutorial III : Nios II processor software development -- Tutorial IV : Nios II processor hardware design -- Operating system support for SOPC design -- Appendix A. Generation of pseudo random binary sequences -- Appendix B. Quartus II design and data file extensions -- Appendix C. Common FPGA pin assignments -- Appendix D. ASCII character code -- Appendix E. Common I/O connector pin assignments
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